I/O devices

Characterized by behavior

• Input : keyboard
• Output : monitor, printer, NIC
• Storage: disk, cd-rom, flash-drive

IO Controller

• Control/Status registers
  • CPU tells device what to do – write to control register
  • CPU checks whether task i done – read status register

Data registers

• A map of output data to memory map

Device electronics

• Performs actual operaiton
• pixels to screens, bit to/from disk, characters from keyboard

Issues

• How are device registers identified
  • mem mapped io vs special io
• How is timing of data transfer managed
  • Async vs sync

Who controls transfer

• CPU (polling) vs. devices (interrupts)

Memory map IO vs special instructions IO

• Instructions
  • Designated opcode for IO
  • register and operation encoded in instruction
• Memory mapped
  • assign a memory address to each device register
  • use data movement instructions (LD/ST) for control and data transfer

Transfer timing

• IO events generally happen much slower than CPU cycles

Synchronous

• Data supplied at a fixed predictable rate
• CPU reads/writes every X cycles

Asynchronous

• Data rate isn’t predictable in Asynchronous
• CPU must synchonize with device so it doesnt miss data

Transfer Control

• Who determines when the next data transfer occurs

• Polling(CPU is proactive )
  • CPU keeps checking status register until new data arrives or devices ready for next data
  • “Are we there yet?”
• Interrupts (device is proactive )
  • Device sends a special signal to CPU when new data arrives or device ready for next data
  • CPU can be performing other tasks instead of polling devices
  • “Wake me when we get there”

Input from keybard

• When a character is types its ASCII code is placed in the KBDR bits [7:0]

Discussion

A. Remote control and television set – Synchronous B. Mail postman and you via mailbox – async C. Mouse and PC – Synchronous

Testing for interupt sinal

• CPU looks at signal between store and fetch phases
• If not set, continues with the next instruction
• If set, transfers control to interrupt service routine

If something can’t be interupted from begining to end then it is known as atomic

Priority

• Every instruction executes a stated level of urgency