ISA - Instruction Set Architecture

• Defines what the processor is capable of processing
• Specifies
  • Memory
  • instructions

Question

Given an address x3006

What is the page id? And what is the offset to the page

3      0     0     6
0011  000|0  0000   0110
PID ID   | OFFSET  

Only three operations - ADD AND NOT

NOT

[Oppcode][Operands[Padding]]

SRC and DST can refer to the same resiter

Using operate instructions

• With only ADD, AND, NOT - how do we copy from one register R2 to another R3 (One add instruction)
  • Set R3 to zero and add R2 to it
  • ADD R3, R2, #0
• How do we set a register R2 to zero (one and instruction )
  • And it with zero
  • AND R2, R2, #0
• How do we subtract R1 R2 R3 (R1 is the destination)
  • NOT R3 R3
  • ADD R3 R3, #1
  • ADD R1 R2 R3
• How do we OR (OR R3 R1 R2)
  • R2 + R2
  • NOT R1, R1
  • ADD R1, R1, #2
  • NOT R2, R2
  • ADD R2, R2 #1
  • ADD R3, R2, R1

  R3 = R2 + R1
  ~[R2 + R1] = ~R2*~R1
  

Data movement instructions

• Load
  • LD
  • LDR
  • LDI
• Store
• Load effective address

PC-Relative addressing mode

LOAD

A load operation takes something from memory and puts it in a register [op code][Destination register][PC-Offset] 4 bits 3 bits 9 bits

PC Counter is added to the LD

LDR (Base + Offset)

[0110][DST][BSE][OFFSET] Load content of memory of an offset x1D with respect to R2 to R1

R1 = MEM[R2+ offset]

There are only 8 registers to work with.

LDR (PC-Relative)

R2 = MEM[PC + PC Offset] R1 = MEM[R2 + Offset]

Indirect Adressing Mode

Its like using a spot in array as an index for another spot in the array. R3 = MEM[MEM[PC + PC Offset]];

Question

How to copy a memory content at location x3011 to another location x3010

0010 000 0 0001 0000 (offset is x10) PC = x3001 0011 000 0 0000 1110 (offset is xE) PC = x3002

Store (as opposed to load)

• ST –> LD
• STI –> LDI
• STR

ST

MEM[PC + PC Offset] = R2

STI

MEM[MEM[PC + PC Offset]] = R3

STR (Base + Offset)

MEM[R2 + Offset] = R1

LEA

Compute an address, save it in a register.

[LEA][DST Register][PC - OFFSET]

• Example
  • Load the address PC-3 to register R5 [1110][101][111111101]

PC

If address x30F6 is executing then the program counter is at x30f7.

Branches

Branch

[0000][NZP][PC-OFFSET]

[0000][010][011011001] if the last thing stored is zero this instruction will jump to the program counter + PC-OFFSET

If the nzp is all ones then it is an unconditional branch.

if (x == 0) {

}

add r0, r0, #0
br  pb

Jump instruction

An unconditional branch – Always taken

[1100][000][BSR][00000]

Trap Instruction

Calls a service routine, identified by -bit “trap vector”

These are part of the operating system

Labels

You don’t need the PC offset with a label

.ORIG x3050
LD R1, SIX
LD R2, NUMBER
AND R3, R3, #0

; AGAIN acts at the label here
AGAIN ADD r3, R3, R2
      ADD R1, R1, #-1
      Brp AGAIN

HALT

NUMBER .BLKW
SIX .FILL x006
.END

LABEL OPCODE OPERANDS COMMENTS

Assembler Directives

• Pseudo-operations
  • Does not refer to operations executed by the program
  • Used by the assembler *Looks like instrcution but the opcode satrts with a dot

Trap codes

• HALT - Trap x25
• IN print promtp on the console

Storing a string

x305C  c .STRINGZ "CatDog"
x305D  a
x305e  t
x305f  D
x3060  o
x3051  g

Three major components of an assembly program

• Comments
• Instructions

• Directives

• Labels refer to memory locations

.Fill

loading constants into memory locations

Compilation process

There are two passes when an assembly program is compiled.

• First pass:
  • find all labels and calculate corresponding addresses put into something called a Symbolic table
• Second pass:
  • For each executable assembly language statement, generates the corresponding machine language instruction

Buffer overflow

Spots in memory that contain instructions are overwritten

Loading v Linking

Loading

THe process of copying an executable image into memory

Linking

Process of resolving symbols between independent object files